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KM23V32005BG
32M-Bit (4Mx8 /2Mx16) CMOS MASK ROM
FEATURES
* Switchable organization 4,194,304x8(byte mode) 2,097,152x16(word mode) * Fast access time Random Access Time : 100ns(Max.) Page Access Time : 30ns(Max.) * 8 words / 16 bytes page access * Supply voltage : single +3.3V * Current consumption Operating : 60mA(Max.) Standby : 30A(Max.) * Fully static operation * All inputs and outputs TTL compatible * Three state outputs * Package KM23V32005BG : 44-SOP-600
CMOS MASK ROM
GENERAL DESCRIPTION
The KM23V32005BG is a fully static mask programmable ROM fabricated using silicon gate CMOS process technology, and is organized either as 4,194,304x8 bit(byte mode) or as 2,097,152x16 bit(word mode) depending on BHE voltage level.(See mode selection table) This device includes page read mode function, page read mode allows 8 words(or 16 bytes) of data to read fast in the same page, CE and A3 ~ A20 should not be changed. This device operates with a 3.3V power supply, and all inputs and outputs are TTL compatible. Because of its asynchronous operation, it requires no external clock assuring extremely easy operation. It is suitable for use in program memory of microprocessor, and data memory, character generator. The KM23V32005BG is packaged in a 44-SOP.
FUNCTIONAL BLOCK DIAGRAM
A20 . . . . . . . . A3 A0~A2 A-1 X BUFFERS AND DECODER MEMORY CELL MATRIX (2,097,152x16/ 4,194,304x8)
PIN CONFIGURATION
N.C A18 A17 A7 A6 A5
1 2 3 4 5 6 7 8 9 11
44 A20 43 A19 42 A8 41 A9 40 A10 39 A11 38 A12 37 A13 36 A14 35 A15 34 A16 33 BHE 32 VSS 31 Q15/A-1 30 Q7 29 Q14 28 Q6 27 Q13 26 Q5 25 Q12 24 Q4 23 VCC
Y BUFFERS AND DECODER
SENSE AMP. DATA OUT BUFFERS ...
A4 A3 A2 A0
A1 10 CE 12 VSS 13 OE 14 Q0 Q8 15 16
SOP
CE OE BHE CONTROL LOGIC Q0/Q8 Q7/Q15
Q1 17 Q9 18 Q2 19 20 Q10
Pin Name A0 - A2 A3 - A20 Q0 - Q14 Q15 /A-1 BHE CE OE VCC VSS N.C
Pin Function Page Address Inputs Address Inputs Data Outputs Output 15(Word mode)/ LSB Address(Byte mode) Word/Byte selection Chip Enable Output Enable Power (3.3V) Ground No Connection
Q3 21 Q11 22
KM23V32005BG
KM23V32005BG
ABSOLUTE MAXIMUM RATINGS
Item Voltage on Any Pin Relative to VSS Temperature Under Bias Storage Temperature Symbol VIN TBIAS TStg Rating
CMOS MASK ROM
Unit V C C
-0.3 to +4.5 -10 to +85 -55 to +150
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should berestricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70C)
Item Supply Voltage Supply Voltage Symbol VCC VSS Min 3.0 0 Typ 3.3 0 Max 3.6 0 Unit V V
DC CHARACTERISTICS
Parameter Operating Current Standby Current(TTL) Standby Current(CMOS) Input Leakage Current Output Leakage Current Input High Voltage, All Inputs Input Low Voltage, All Inputs Output High Voltage Level Output Low Voltage Level Symbol ICC ISB1 ISB2 ILI ILO VIH VIL VOH VOL IOH=-400A IOL=2.1mA Test Conditions CE=OE=VIL, all outputs open CE=VIH, all outputs open CE=VCC, all outputs open VIN=0 to VCC VOUT=0 to VCC 2.0 -0.3 2.4 Min Max 60 500 30 10 10 VCC+0.3 0.6 0.4 Unit mA A A A A V V V V
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
MODE SELECTION
CE H L L OE X H L BHE X X H L Q15/A-1 X X Output Input Mode Standby Operating Operating Operating Data High-Z High-Z Q0~Q15 : Dout Q0~Q7 : Dout Q8~Q14 : Hi-Z Power Standby Active Active Active
CAPACITANCE(TA=25C, f=1.0MHz)
Item Output Capacitance Input Capacitance Symbol COUT CIN Test Conditions VOUT=0V VIN=0V Min Max 12 12 Unit pF pF
NOTE : Capacitance is periodically sampled and not 100% tested.
KM23V32005BG
TEST CONDITIONS
Item Input Pulse Levels Input Rise and Fall Times Input and Output timing Levels Output Loads Value
CMOS MASK ROM
AC CHARACTERISTICS(TA=0C to +70C, VCC=3.3V0.3V, unless otherwise noted.)
0.45V to 2.4V 10ns 1.5V 1 TTL Gate and CL=100pF
READ CYCLE
Item Read Cycle Time Chip Enable Access Time Address Access Time Page Address Access Time Output Enable Access Time Output or Chip Disable to Output High-Z Output Hold from Address Change
NOTE : Page Address is determined as below. Word mode(BHE=VIH) ; A0, A1, A2 Byte mode(BHE=VIL) ; A -1, A0, A1, A2
Symbol tRC tACE tAA tPA tOE tDF tOH
KM23V32005BG-10 Min 100 100 100 30 30 20 0 Max
KM23V32005BG-12 Min 120 120 120 50 50 20 0 Max
KM23V32005BG-15 Min 150 150 150 70 70 30 0 Max
Unit ns ns ns ns ns ns ns
KM23V32005BG
TIMING DIAGRAM
READ
ADD A0~A20 A-1(*1) tACE CE tOE OE tOH DOUT D0~D7 D8~D15(*2) VALID DATA tAA
CMOS MASK ROM
ADD1 tRC
ADD2 tDF(*3)
VALID DATA
PAGE READ
CE
tDF(*3)
OE
ADD A0,A1,A2 A -1(*1) tAA DOUT D0~D7 D8~D15(*2)
1 st tPA VALID DATA
2 nd
3 rd
VALID DATA VALID DATA VALID DATA
NOTES : *1.Byte Mode only. A-1 is Least Significant Bit Address.(BHE = VIL) *2. Word Mode only.(BHE = VIH) *3. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.

ADD A3~A20
KM23V32005BG
PACKAGE DIMENSIONS
44-SOP-600
#44 #23
CMOS MASK ROM
(Unit : mm/inch)
0~8
16.040.30 12.600.20 0.6310.012 0.4960.008
15.24 0.600 0.800.20 0.0310.008 0.10 MAX 0.004 MAX
#1
#22
+0.10 -0.05 0.008+0.004 -0.002
0.20 2.800.20 0.1100.008 3.10 0.122 MAX
28.95 MAX 1.140 28.500.20 1.1220.008
( 0.915 ) 0.036
+0.100 -0.050 +0.004 0.016 -0.002
0.40
1.27 0.050
0.05 MIN 0.002

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